The present invention relates generally to a semiconductor device and method of manufacturing the same and more particularly to a semiconductor device that may have an insulating film embedded in a concave portion formed in a semiconductor substrate and a method of forming the same.
It is a continuing goal to increase the integration level of semiconductor devices. In order to do so, it is desirable to make device structures and device isolation structures smaller. One method of providing smaller device isolation structures is to use a trench isolation structure in place of a conventional local oxidation of silicon (LOCOS) method.
A conventional trench isolation method will now be described with reference to FIGS. 7 and 8. The conventional trench isolation method includes forming a concave portion or trench inside a semiconductor substrate. The trench is etched in a silicon substrate to a depth required for isolation between adjacent devices, forming an insulating film to fill the trench, and then removing the insulating film located outside the trench with a flattening step.
FIGS. 7 and 8 are cross-sectional diagrams of a conventional trench isolation structure after various process steps.
Referring now to FIG. 7(a), a silicon oxide film 102 and a silicon nitride film 103 are formed sequentially on a silicon substrate 101. Next, a resist pattern (not shown) is formed and etched to expose silicon nitride film 103 located over a region (non-active region) where a trench is to be formed. Then, using the resist pattern as a mask, silicon nitride film 103 and silicon oxide film 102 are etched sequentially until the surface of silicon substrate 101 is exposed. The resist pattern is then removed, the exposed silicon substrate 101 is etched using silicon nitride film 103 as a mask to form a trench T.
Referring now to FIG. 7(b), a thermal oxide film 104 is formed on the inner wall surface of trench T. Thermal oxide film 104 helps to compensate for damage to the surface of the substrate 101 caused the above-mentioned etching carried out to form trench T. Thermal oxide film 104 also helps to prevent dislocation from occurring inside the substrate 101 by rounding off the corners of trench T to relieve stress.
Referring now to FIG. 7(c), a nitride film liner 105 is then formed over the surface and an embedding insulating film 106 is then formed on the surface to fill trench T. Nitride film liner 105 is formed to prevent oxygen from infiltrating inside the wall of trench T through embedding insulating film 106 in a subsequent oxidation step, or the like. In this way, the trench walls may be prevented from being further oxidized. If oxygen infiltrates the wall of trench T, silicon in that portion is oxidized and increases in volume to produce stress. This can cause defects such as dislocation, or the like, which can cause device characteristics to deteriorate.
Referring now to FIG. 8(a), chemical mechanical polishing (CMP) is carried out until silicon nitride film 103 is exposed to flatten the surface of the substrate.
Referring now to FIG. 8(b), silicon nitride film 103 formed over the region (active region) other than the non-active region of the substrate 101 is removed by wet etching. At this time, if the thickness of nitride film liner 105 is thick, nitride film liner 105 is etched deep inside the trench. As will be illustrated later, this causes a groove to be formed in this region in a subsequent step.
Referring now to FIG. 8(c), silicon oxide film 102 over the active region and a protruding portion of embedding insulating film 106 in the non-active region are removed in a wet washing step (wet etching) to form a target trench isolation structure. At this time, a groove D is formed along the edge of the device isolation region (trench isolation region) formed with the insulating film embedded in the trench. Groove D is caused due to a part of nitride film liner 105 being etched inside the trench (illustrated in FIG. 8(b)).
When groove D is deep and/or wide, an electrically conductive material tends to remain inside groove D in a later step of forming gate electrode. This can cause short circuit failure in these gate electrodes. Also, the electric field of the gate electrodes can be increased in the substrate corners defined by groove D. Such an increased electric field causes instability in device characteristics, such as threshold voltage, which causes undesirable effects such as an increase of leakage currents, or the like. In order to suppress the formation of groove D, it is desirable that nitride film liner 105 has a relatively thin film thickness.
Japanese Patent Application Laid-Open No. 2000-12677 (JPA 12677) describes a method of forming a conventional trench isolation structure such that groove D may be suppressed. A conventional trench isolation structure disclosed in JPA 12677 will be discussed with reference to FIGS. 9 and 10.
Referring now to FIG. 9(a), silicon oxide film 102 and silicon nitride film 103 are formed on substrate 101. Silicon nitride film 103 is then patterned and etched. Etching the exposed surface of substrate 101 to form trench T is done in the same manner as the conventional approach illustrated in FIG. 7(a). Thermal oxide film 104 is then formed on an inner wall of trench T in the same manner as previously described and illustrated in FIG. 7(b).
Referring now to FIG. 9(b), silicon nitride film 103 is isotropically etched by a predetermined thickness. By isotropic etching, not only the upper surface of silicon nitride film 103, but also lateral surface portions are etched. In this way, the diameter of the opening in silicon nitride film 103 is enlarged with respect to that of trench T. As a result, a brim-like portion where the surface of substrate 101 or oxide film 102 is exposed around the opening portion of trench T and a step-like shape is obtained.
Referring now to FIG. 9(c), nitride film liner 105 is formed on the surface of substrate 101 in the same manner as previously described and illustrated in FIG. 7(c). Then, embedding insulating film 106 is formed so as to fill the inside of trench T.
Referring now to FIG. 10(a), CMP is carried to planarize the surface and expose the silicon nitride film 103 in the same manner as previously discussed and illustrated in FIG. 8(a).
Referring now to FIG. 10(b), silicon nitride film 103 is removed by isotropic etching (wet etching). During the isotropic etching, nitride film liner 105 is also gradually removed from the exposed edge. However, because the brim-like portion serves as a buffer, excessive etching which reaches the inside of the trench is prevented even though nitride film liner 105 on the brim-like portion is removed by etching. Thus, groove D is prevented from being formed in the wet washing step and trench isolation structure is formed as illustrated in FIG. 10(c).
The above-mentioned JPA 12677 reference discloses an alternative way of forming a brim-like portion around the opening edges of trench T in another embodiment as will be discussed with reference to FIG. 11.
Referring now to FIG. 11(a), after silicon oxide film 102 and silicon nitride film 103 are sequentially etched to form an opening so as to expose a surface silicon substrate 101 in an inactive region, an oxide film is formed on the entire surface. The oxide film is then etched back by anisotropic etching to form spacers 107 on lateral walls of the opening.
Referring now to FIG. 11(b), the exposed portion of substrate 101 is etched using spacers 107 and silicon nitride film 103 as masks to form trench T.
After removal of spacers 107, a thermal oxide film is formed on the inner wall of trench T. In this way, a step-like shape similar to that illustrated in FIG. 9(b) is obtained where a brim-like portion is formed around the opening portion of the trench T.
In order to ensure a sufficient width in the brim-like portion using the method described in the above-mentioned JPA 12677, it is necessary to either increase the amount of wet etching for the nitride film so as to enlarge the opening in the silicon nitride film 103 shown in FIG. 9(b) or to thicken spacers 107 shown in FIG. 11(a). However, if the amount of wet etching for the nitride film is increased, silicon nitride film 103 is thinned. This can reduce the effectiveness of the silicon nitride film 103 as a polishing stopper in the later CMP step. On the other hand, ensuring a sufficient width of spacers 107 prevents the reduction in the width of the active region between trenches, which reduces the miniaturization of the device and increases production costs.
Also, because it is difficult to uniformly form the width of the brim-like portion due to manufacturing fluctuations, the nitride film liner 105 formed on the brim-like portion may not be completely removed in the nitride film wet etching step and may partially remain in the active region. The remaining nitride film liner 105 on the active region can cause etching of the oxide film underlying the nitride film liner 105 in the oxide film wet etching step. As a result, a part of the nitride film liner 105 may remain resulting in an eave-like portion 108 as illustrated in FIG. 12. In a later step of forming a gate pattern, a gate electrode material or the like is likely to remain under the eave-like portion 108 of nitride film liner 105. This may result in a short circuit between gate electrodes.
In view of the above discussion, it would be desirable to provide a method of forming a trench isolation structure for a semiconductor device in which the formation of a groove along the edge of a trench region may be suppressed. It would also be desirable to provide a method of forming a trench isolation structure for a semiconductor device in which an undesired device material may be prevented from remaining in a region of the trench isolation structure during the formation of a gate pattern or the like. It would also be desirable to provide the above qualities while obtaining desired device characteristics and device isolation characteristics. It would also be desirable to provide a semiconductor device including a trench isolation structure including the above qualities.
According to the present embodiments, a semiconductor device including an insulating film embedded in a concave portion, such as a trench formed on a semiconductor substrate is disclosed. A method of forming a trench isolation structure may include forming a mask layer having a predetermined opening pattern. The mask layer may include a nitride film. A trench may be formed through etching using a mask layer as a mask. A thermal oxide film may be formed on an inner wall of a trench. An insulating film may be formed on an entire main surface of a semiconductor substrate. Insulating film may provide an etching barrier. A nitride film liner may be formed on an insulating film. An embedding insulating film may be formed so as to essentially fill trench. A planarization treatment may be conducted so as to expose nitride film. Nitride film may then be removed by isotropic etching. In this way, a formation of a groove along an edged of a trench isolation structure may be suppressed while sufficient device characteristics may be obtained.
According to one aspect of the embodiments, a method of forming a trench isolation structure in a semiconductor device may include the steps of forming a masking layer including an first oxidation-resistant insulating film on a semiconductor substrate and then forming a predetermined opening in the mask layer, etching an exposed portion of the semiconductor substrate using at least the mask layer as a mask to form a trench, forming a first insulating film on an inner wall of the trench, forming an etching barrier layer on at least a side portion of the mask layer at the predetermined opening pattern, forming a second oxidation-resistant insulating film on the inner wall of the trench including on the etching barrier layer, forming a second insulting film to essentially fill the trench, conducting a planarization treatment so that the first oxidation-resistant insulating film of the mask layer may be exposed, and removing a mask layer by etching.
According to another aspect of the embodiments, a method of forming a trench isolation structure in a semiconductor device may include the steps of forming a masking layer including an first oxidation-resistant insulating film on a semiconductor substrate and then forming a predetermined opening in the mask layer, forming an insulating film on a main surface of the semiconductor substrate and etching back the insulating film by anisotropic etching to form a sidewall on a lateral wall of the inside of the opening pattern in the mask layer, etching an exposed portion of the semiconductor substrate using at least the mask layer as a mask to form a trench, forming a first insulating film on an inner wall of the trench, forming a second oxidation-resistant insulating film on the inner wall of the trench including on the etching barrier layer, forming a second insulting film to essentially fill the trench, conducting a planarization treatment so that the first oxidation-resistant insulating film of the mask layer may be exposed, and removing a mask layer by etching.
According to another aspect of the embodiments, a semiconductor device including a trench isolation structure may include a trench formed in a semiconductor substrate. A second insulating film may be formed on a first insulating film. An oxidation insulating film may be formed on the second insulating film. An anti-static insulating film may be formed on an oxidation-resistant insulating film in a trench. An embedding insulating film may be formed to essentially fill an inside of a trench including the first insulating film, the second insulating film, the oxidation-resistant insulating film, and the anti-static insulating film.
According to another aspect of the embodiments, an exposed edge of a second oxidation-resistant barrier layer may be etched when a mask layer is removed by etching.
According to another aspect of the embodiments, an etching barrier layer may be formed on inner walls of the trench and at least a side portion of a mask layer.
According to another aspect of the embodiments, an etching barrier layer may include an oxide film having a thickness of about 5 nm to 30 nm.
According to another aspect of the embodiments, a first oxidation-resistant film may include a second nitride film having a thickness of about 4 nm to 20 nm.
According to another aspect of the embodiments, a method of forming a trench isolation structure may include forming an anti-static insulating film on the second oxidation-resistant insulating film by a thermal chemical vapor deposition (CVD) method. A second insulating film may be formed by a plasma CVD method.
According to another aspect of the embodiments, a plasma CVD method may be a high-density plasma CVD method.
According to another aspect of the embodiments, an anti-static insulating film may include an oxide film having a thickness of about 5 nm to 30 nm.
According to another aspect of the embodiments, a first insulating film may include a thermal oxide film.
According to another aspect of the embodiments, a sidewall may include an oxide film having a thickness of about 10 nm to 100 nm.